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Integrate linux-seco-imx/niccolor/c61-edp

Git Bot Service Account requested to merge linux-seco-imx/niccolor/c61-edp into kirkstone

Commit: clea-os/bsp/nxp/linux-seco-imx@4e7257c8

[PATCH] drm/bridge: seco-sn65dsi86: Add retries for link training

This is a porting of the patch: https://github.com/nxp-imx/linux-imx/commit/137655d1ed353806b8591855b569efd090d84135#diff-b3bd3abc4d5a92f5ab51f7969161a7aa63e53cfb0db8a6c1be21fca7581bbf6dR109

On some panels hooked up to the ti-sn65dsi86 bridge chip we found that link training was failing. Specifically, we'd see:

ti_sn65dsi86 2-002d: [drm:ti_sn_bridge_enable] ERROR Link training failed, link is off (-5)

The panel was hooked up to a logic analyzer and it was found that, as part of link training, the bridge chip was writing a 0x1 to DPCD address 00600h and the panel responded NACK. As can be seen in header files, the write of 0x1 to DPCD address 0x600h means we were trying to write the value DP_SET_POWER_D0 to the register DP_SET_POWER. The panel vendor says that a NACK in this case is not unexpected and means "not ready, try again".

In testing, we found that this panel would respond with a NACK in about 1/25 times. Adding the retry logic worked fine and the most number of tries needed was 3. Just to be safe, we'll add 10 tries here and we'll add a little blurb to the logs if we ever need more than 5.

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Commit: clea-os/bsp/nxp/linux-seco-imx@fc455f70

[C61][DTO][EDP] sn65dsi86 fix edp signals timings and order

  • now the backlight correctly start after the bridge

  • the correct sequence is:

    1. VCC_LCD_EN (pca6416_20 5)
    2. iMX8_LVDS_BKL_ON (gpio4 4)
    3. VCC_BKL_EN (pca6416_20 9)

  • also remove some edp_bridge parameters not present in the seco-sn65dsi86 driver

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Commit: clea-os/bsp/nxp/linux-seco-imx@db056021

[C61][DTO][EDP] sn65dsi86 remove explicit declaration of the clock

If we look at the hw design of the board the SN65DSI86 should use the external clock REFCLK. However, for some reasons (maybe also an error), the corresponding clock generator SI5351A has never been declared even in the old kernels used for the signal integrity and emission test; so no REFCLK is present in the corresponding SN65DSI86 pin. What happen is that the SN65DSI86 automatically detect that there is no clock in the REFCLK pin and so try to get DP PLL from the DSI DACP/N pins, even if inside the driver the code try to set the clock based on the "clocks = <&osc_27m>" parameter that explicit a REFCLK.

Somehow this condition work most of the time, but there are some boards where this condition bring to an error during the "Link training" of the edp: [drm:ti_sn_bridge_enable] ERROR Link training failed, link is off

With the hw team has been decided to just remove the declaration of the REFCLK in the dts so that the driver correctly set the refclk frequency (ti_sn_bridge_set_refclk_freq function) and fix the "link training" error. This decision is to not change the condition of the board compared to the signal integrity and the emission test

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